Designing my own TPU for transformer inference: a summer project building an int4 transformer accelerator on a Cmod A7 FPGA, then optimizing the kernels (FlashAttention included) and deriving single-device scaling results. [code]
Research
SumCATS: a CUDA implementation of the sum-check protocol over binary fields, 1.81× faster than the previous best GPU implementation. First-authored, accepted to IEEE DATE 2026. [paper] [code]
Engineering Leadership
Paly Robotics (FRC Team 8), Software Lead: led a 12-person software subteam for a world top-200 robot across 8 subsystems, and rewrote the codebase to an event-driven architecture that runs in simulation. First event win in 6 years at the 2026 Contra Costa District event! team 8 github
Honors
USA Computing Olympiad, Platinum Division; perfect score (1000/1000) in the 2023 December Gold contest